Some communications network devices are required either by government or network regulations or protocols to remain fully powered during undervoltage or power outage conditions for a time period that depends on the product and application. This length of time can be 2 ms to 25 ms in some applications, but can be as high as 50 ms in other applications. Conventional circuit solutions add bulk input capacitance to prolong the time between when power is lost and when the minimum operating voltage threshold is reached by reducing the input voltage slew rate. For some applications, however, this approach is impractical.
As power demands and hold-up times increase and minimum operating input voltages decrease, the input capacitance required to satisfy these constraints becomes so large that the capacitors consume more printed circuit board (PCB) area than is practical or even available. One known telecommunications device is required to hold up to 20 watts of power for 24 milliseconds at a minimum specified operating voltage of 20V and an undervoltage shutoff threshold at 18V. To meet these requirements would require 0.013 Farads worth of capacitance, which would not be practical from both a cost and PCB area standpoint.
There are other hold-up circuits that address these issues and are generally known for boosting input voltage. These known hold-up circuits rely on their own boost power supply controllers, however. Other circuits support a “dying gasp” signal, for example, circuitry disclosed in U.S. Pat. No. 7,302,352; U.S. Patent Publication No. 2008/0046768; and U.S. Pat. Nos. 7,098,557 and 7,355,303.